Chapter 11 discusses FTTC and FTTH networks. This chapter has been limited to options within conventional HFC networks. The relationship between architecture, network reliability, and network availability is a major topic in itself. But just as important is the ability to scale to meet market demand and opportunities without “stranding” capital and without causing excessive service interruptions to existing customers because of required reconfiguration. In considering an architecture, initial cost is certainly a factor. In the largest systems, both structures may be used in multitiered architectures. It is possible to “push” much signal processing out to hubs in order to increase the efficiency of the headend-to-hub links, or to centralize the processing for easier management at the expense of needing more fiber capacity. Coaxial amplifier cascades vary from 1 to 6 in typical new upgrades. Single coaxial cable low-split-band plans are used in the vast majority of systems, with individual nodes serving 400 to 1000 homes.
In large regional systems, formerly independent headends are often linked by either digital or 1550-nm analog, fiber-optic links to a large master headend and become hubs. The most common small-system architecture in use today is the single star, with nodes connected directly to a single headend.
The examples given illustrate choices made or proposed to meet specific service requirements in specific service areas. This chapter has described some of the architectural elements and how each is related to essential network characteristics. It controls effective bandwidth, reliability, flexibility, and distribution of signal processing. The architecture of a system determines the services it can deliver.
#BANDWIDTH COMPUTER DEFINITION CODE#
Compared to the value of 145 GB/s from Table 2.1, we once again do not expect to obtain any further substantial speedups for this code on this device.ĭavid Large, James Farmer, in Broadband Cable Access Networks, 2009 10.4 Summary To obtain the effective bandwidth for this kernel on the Tesla K20, once again with ECC on, we simply substitute the profiler time for the base kernel of 481 μ s into the preceding formula to obtain a value of 139 GB/s. As a result, we do not expect to obtain any further substantial speedups for this code on this device. Instead we use the appropriate number of 107 GB/s from Table 2.1. We could compare this result to the theoretical peak bandwidth for the C2050 of 144 GB/s, but this does not account for ECC effects. The profiler results for the base kernel give a GPU time of 635 μ s, which results in an effective bandwidth of roughly 106 GB/s. The number of elements is multiplied by the size of each element (4 bytes for a float), multiplied by 2 (because of the read and write), divided by 10 9 to obtain the total GB of memory transferred.
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